| 1. | Logic synthesis logic synthesizer
逻辑合成逻辑合成器 |
| 2. | ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "
( 4 )设计并实现了“多级逻辑综合延迟均衡”算法。 |
| 3. | 2 . the logic synthesis process is studied in detail and the relative constraints are discussed
2 .详细研究了soc应用设计流程中的逻辑综合技术方法。 |
| 4. | 2002 , 149 : 119 - 128 . 9 sasao t . switching theory for logic synthesis . kluwer academic publishers , london , 1999
通过对给定的fprm真值矢量进行收缩,获得收缩后的真值矢量,然后把该矢量映射成逻辑表示式。 |
| 5. | This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization
论文详细讨论了低功耗有限状态机综合与优化中的符号逻辑和一些典型方法。 |
| 6. | Finally , their applications in the logic synthesis based on the partial linear function and calculating boolean difference of logical functions are discussed
最后讨论了它们在逻辑综合以及计算逻辑函数的布尔差分中的应用。 |
| 7. | Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。 |
| 8. | At last , the paper involves the flow and related data of logic simulation , logic synthesis and test vector in the risc cpu
论文最后给出了64位vegacpu的asic逻辑仿真文件和仿真波形，逻辑综合策略、综合脚本和综合结果，以及vegacpu基于atpg的测试向量设计流程和相关数据。 |
| 9. | The design phase includes the standardization of rtl coding , logic synthesis and place & route ; the verification phase includes the function verification , static timing analysis and physical verification for 08c01
设计工作包括对08c01软核的rtl级代码标准化、逻辑综合和布局布线；验证工作包括对08c01软核的功能验证、静态时序分析和物理验证。 |
| 10. | By the top - down way , the design was divided into several modules according to their functions , which were characterized respectively . meanwhile , behavior description , rtl function simulation and logic synthesis were carried out
在充分了解驱动电路系统的基础上,采用“自上向下”的设计方法将其划分为几个功能模块,并对它们分别进行了行为描述、 rtl功能仿真、逻辑综合。 |
